How to enable SSP clock?

Windows CE 5.0
Intel PXA 270

In ssp/spi driver, I want to enable the ssp1 clock, but I don't know
how to do.

Here is the same problem:

http://groups.google.com/group/microsoft.public.windowsce.platbuilder/browse_thread/thread/65e8883348499967/1e88f30d6f9f38a1?lnk=gst&q=clock+enable+spi&rnum=3&hl=zh-CN#1e88f30d6f9f38a1

Can anybody explain it in detail?

Thanks in advance!

Henrik
Fri Nov 24 01:36:11 CST 2006

It's pretty trivial, really. You just have to map it up and set the
correct bit in the cken register. Using select pxa27x CSP headers it
could look something like this:

static XLLP_CLKMGR_T* g_pClkRegs;
...

PHYSICAL_ADDRESS ioPhysicalBase = {BULVERDE_BASE_REG_PA_CLKMGR,0};
g_pClkRegs = (XLLP_CLKMGR_T *)MmMapIoSpace(ioPhysicalBase,
sizeof(XLLP_CLKMGR_T),FALSE);

...

g_pClkRegs->cken |= SPIEnableBit;

...

What bit you need to set I leave as an excersise for you to complete
(see the clock manager section in the PXA27x developer's manual...).

Henrik Viklund
http://www.addlogic.se


campos skrev:

> Windows CE 5.0
> Intel PXA 270
>
> In ssp/spi driver, I want to enable the ssp1 clock, but I don't know
> how to do.
>
> Here is the same problem:
>
> http://groups.google.com/group/microsoft.public.windowsce.platbuilder/browse_thread/thread/65e8883348499967/1e88f30d6f9f38a1?lnk=gst&q=clock+enable+spi&rnum=3&hl=zh-CN#1e88f30d6f9f38a1
>
> Can anybody explain it in detail?
>
> Thanks in advance!

vlick
Fri Nov 24 10:14:57 CST 2006


In addition to what Henrik said, be sure to manage correctly the "sse"
bit (as described on documentation) who enable/disable the SSP
functionality.

regards

Vlick

campos
Sat Nov 25 03:59:02 CST 2006

Thanks~

I looked the datasheet of PXA270 for the base address:
#define BULVERDE_BASE_REG_PA_CLKMGR 0x41300000
and I just did what you told me.

But it seemed to be an error during the MemMap.
I just changed to VirtualAlloc() and VirtualCopy() and I found error in
the latter.

Would you please give me some hints?

Thanks~

"Henrik Viklund =D0=B4=B5=C0=A3=BA
"
> It's pretty trivial, really. You just have to map it up and set the
> correct bit in the cken register. Using select pxa27x CSP headers it
> could look something like this:
>
> static XLLP_CLKMGR_T* g_pClkRegs;
> ...
>
> PHYSICAL_ADDRESS ioPhysicalBase =3D {BULVERDE_BASE_REG_PA_CLKMGR,0};
> g_pClkRegs =3D (XLLP_CLKMGR_T *)MmMapIoSpace(ioPhysicalBase,
> sizeof(XLLP_CLKMGR_T),FALSE);
>
> ...
>
> g_pClkRegs->cken |=3D SPIEnableBit;
>
> ...
>
> What bit you need to set I leave as an excersise for you to complete
> (see the clock manager section in the PXA27x developer's manual...).
>
> Henrik Viklund
> http://www.addlogic.se
>
>
> campos skrev:
>
> > Windows CE 5.0
> > Intel PXA 270
> >
> > In ssp/spi driver, I want to enable the ssp1 clock, but I don't know
> > how to do.
> >
> > Here is the same problem:
> >
> > http://groups.google.com/group/microsoft.public.windowsce.platbuilder/b=
rowse_thread/thread/65e8883348499967/1e88f30d6f9f38a1?lnk=3Dgst&q=3Dclock+e=
nable+spi&rnum=3D3&hl=3Dzh-CN#1e88f30d6f9f38a1
> >=20
> > Can anybody explain it in detail?
> >=20
> > Thanks in advance!

Henrik
Sat Nov 25 06:15:42 CST 2006

While I havn't run that exact code snippet myself I'd say VirtualAlloc,
VirtualCopy and MmMapIoSpace are all pretty thorouhgly tested functions
;-) Exactly what do you mean with "found an error"? It dosn't compile?
It dosn't map right? The SPI port still dosn't work?

Anyway, you'll find all the pxa27x base address definitions and lots of
other goodies in the pxa27x CSP
(\WINCE600\PUBLIC\COMMON\OAK\CSP\ARM\INTEL\PXA27X). I think you'll find
atleast couple of examples of mapping up the clock controller. Good
luck.

Henrik Viklund
http:://www.addlogic.se

campos skrev:

> Thanks~
>
> I looked the datasheet of PXA270 for the base address:
> #define BULVERDE_BASE_REG_PA_CLKMGR 0x41300000
> and I just did what you told me.
>
> But it seemed to be an error during the MemMap.
> I just changed to VirtualAlloc() and VirtualCopy() and I found error in
> the latter.
>
> Would you please give me some hints?
>
> Thanks~
>
> "Henrik Viklund =D0=B4=B5=C0=A3=BA
> "
> > It's pretty trivial, really. You just have to map it up and set the
> > correct bit in the cken register. Using select pxa27x CSP headers it
> > could look something like this:
> >
> > static XLLP_CLKMGR_T* g_pClkRegs;
> > ...
> >
> > PHYSICAL_ADDRESS ioPhysicalBase =3D {BULVERDE_BASE_REG_PA_CLKMGR,0};
> > g_pClkRegs =3D (XLLP_CLKMGR_T *)MmMapIoSpace(ioPhysicalBase,
> > sizeof(XLLP_CLKMGR_T),FALSE);
> >
> > ...
> >
> > g_pClkRegs->cken |=3D SPIEnableBit;
> >
> > ...
> >
> > What bit you need to set I leave as an excersise for you to complete
> > (see the clock manager section in the PXA27x developer's manual...).
> >
> > Henrik Viklund
> > http://www.addlogic.se
> >
> >
> > campos skrev:
> >
> > > Windows CE 5.0
> > > Intel PXA 270
> > >
> > > In ssp/spi driver, I want to enable the ssp1 clock, but I don't know
> > > how to do.
> > >
> > > Here is the same problem:
> > >
> > > http://groups.google.com/group/microsoft.public.windowsce.platbuilder=
/browse_thread/thread/65e8883348499967/1e88f30d6f9f38a1?lnk=3Dgst&q=3Dclock=
+enable+spi&rnum=3D3&hl=3Dzh-CN#1e88f30d6f9f38a1
> > >
> > > Can anybody explain it in detail?
> > >=20
> > > Thanks in advance!

Bruce
Sat Nov 25 15:38:13 CST 2006

Henrik:

I think you mean \WINCE600\Platform\Common where the CSP code is for CE 6.0.

--
Bruce Eitman (eMVP)
Senior Engineer
beitman AT applieddata DOT net

Applied Data Systems
www.applieddata.net
An ISO 9001:2000 Registered Company
Microsoft WEP Gold-level Member

"Henrik Viklund" <henrik.viklund@gmail.com> wrote in message
news:1164456941.988899.147800@l12g2000cwl.googlegroups.com...
While I havn't run that exact code snippet myself I'd say VirtualAlloc,
VirtualCopy and MmMapIoSpace are all pretty thorouhgly tested functions
;-) Exactly what do you mean with "found an error"? It dosn't compile?
It dosn't map right? The SPI port still dosn't work?

Anyway, you'll find all the pxa27x base address definitions and lots of
other goodies in the pxa27x CSP
(\WINCE600\PUBLIC\COMMON\OAK\CSP\ARM\INTEL\PXA27X). I think you'll find
atleast couple of examples of mapping up the clock controller. Good
luck.

Henrik Viklund
http:://www.addlogic.se

campos skrev:

> Thanks~
>
> I looked the datasheet of PXA270 for the base address:
> #define BULVERDE_BASE_REG_PA_CLKMGR 0x41300000
> and I just did what you told me.
>
> But it seemed to be an error during the MemMap.
> I just changed to VirtualAlloc() and VirtualCopy() and I found error in
> the latter.
>
> Would you please give me some hints?
>
> Thanks~
>
> "Henrik Viklund дµÀ£º
> "
> > It's pretty trivial, really. You just have to map it up and set the
> > correct bit in the cken register. Using select pxa27x CSP headers it
> > could look something like this:
> >
> > static XLLP_CLKMGR_T* g_pClkRegs;
> > ...
> >
> > PHYSICAL_ADDRESS ioPhysicalBase = {BULVERDE_BASE_REG_PA_CLKMGR,0};
> > g_pClkRegs = (XLLP_CLKMGR_T *)MmMapIoSpace(ioPhysicalBase,
> > sizeof(XLLP_CLKMGR_T),FALSE);
> >
> > ...
> >
> > g_pClkRegs->cken |= SPIEnableBit;
> >
> > ...
> >
> > What bit you need to set I leave as an excersise for you to complete
> > (see the clock manager section in the PXA27x developer's manual...).
> >
> > Henrik Viklund
> > http://www.addlogic.se
> >
> >
> > campos skrev:
> >
> > > Windows CE 5.0
> > > Intel PXA 270
> > >
> > > In ssp/spi driver, I want to enable the ssp1 clock, but I don't know
> > > how to do.
> > >
> > > Here is the same problem:
> > >
> > > http://groups.google.com/group/microsoft.public.windowsce.platbuilder/browse_thread/thread/65e8883348499967/1e88f30d6f9f38a1?lnk=gst&q=clock+enable+spi&rnum=3&hl=zh-CN#1e88f30d6f9f38a1
> > >
> > > Can anybody explain it in detail?
> > >
> > > Thanks in advance!

Henrik
Sun Nov 26 07:09:39 CST 2006

Bruce Eitman [eMVP] skrev:

> Henrik:
>
> I think you mean \WINCE600\Platform\Common where the CSP code is for CE 6=
.0.

Ah, I see. Typo... Actually, what I meant to refer to was the PB5 CPU
specific low-level support routines for integrated pheripherals under
"%_WINCEROOT%\PUBLIC\COMMON\OAK\CSP\". (Just for the record, in CE6 I
think all that stuff has been moved to
"%_WINCEROOT%\PLATFORM\COMMON\SRC\SOC\").

Henrik Viklund
http://www.addlogic.se

>
> --
> Bruce Eitman (eMVP)
> Senior Engineer
> beitman AT applieddata DOT net
>
> Applied Data Systems
> www.applieddata.net
> An ISO 9001:2000 Registered Company
> Microsoft WEP Gold-level Member
>
> "Henrik Viklund" <henrik.viklund@gmail.com> wrote in message
> news:1164456941.988899.147800@l12g2000cwl.googlegroups.com...
> While I havn't run that exact code snippet myself I'd say VirtualAlloc,
> VirtualCopy and MmMapIoSpace are all pretty thorouhgly tested functions
> ;-) Exactly what do you mean with "found an error"? It dosn't compile?
> It dosn't map right? The SPI port still dosn't work?
>
> Anyway, you'll find all the pxa27x base address definitions and lots of
> other goodies in the pxa27x CSP
> (\WINCE600\PUBLIC\COMMON\OAK\CSP\ARM\INTEL\PXA27X). I think you'll find
> atleast couple of examples of mapping up the clock controller. Good
> luck.
>
> Henrik Viklund
> http:://www.addlogic.se
>
> campos skrev:
>
> > Thanks~
> >
> > I looked the datasheet of PXA270 for the base address:
> > #define BULVERDE_BASE_REG_PA_CLKMGR 0x41300000
> > and I just did what you told me.
> >
> > But it seemed to be an error during the MemMap.
> > I just changed to VirtualAlloc() and VirtualCopy() and I found error in
> > the latter.
> >
> > Would you please give me some hints?
> >
> > Thanks~
> >
> > "Henrik Viklund =D0=B4=B5=C0=A3=BA
> > "
> > > It's pretty trivial, really. You just have to map it up and set the
> > > correct bit in the cken register. Using select pxa27x CSP headers it
> > > could look something like this:
> > >
> > > static XLLP_CLKMGR_T* g_pClkRegs;
> > > ...
> > >
> > > PHYSICAL_ADDRESS ioPhysicalBase =3D {BULVERDE_BASE_REG_PA_CLKMGR,0};
> > > g_pClkRegs =3D (XLLP_CLKMGR_T *)MmMapIoSpace(ioPhysicalBase,
> > > sizeof(XLLP_CLKMGR_T),FALSE);
> > >
> > > ...
> > >
> > > g_pClkRegs->cken |=3D SPIEnableBit;
> > >
> > > ...
> > >
> > > What bit you need to set I leave as an excersise for you to complete
> > > (see the clock manager section in the PXA27x developer's manual...).
> > >
> > > Henrik Viklund
> > > http://www.addlogic.se
> > >
> > >
> > > campos skrev:
> > >
> > > > Windows CE 5.0
> > > > Intel PXA 270
> > > >
> > > > In ssp/spi driver, I want to enable the ssp1 clock, but I don't know
> > > > how to do.
> > > >
> > > > Here is the same problem:
> > > >
> > > > http://groups.google.com/group/microsoft.public.windowsce.platbuild=
er/browse_thread/thread/65e8883348499967/1e88f30d6f9f38a1?lnk=3Dgst&q=3Dclo=
ck+enable+spi&rnum=3D3&hl=3Dzh-CN#1e88f30d6f9f38a1
> > > >
> > > > Can anybody explain it in detail?
> > > >
> > > > Thanks in advance!

campos
Mon Nov 27 12:16:38 CST 2006

Thanks Henrik,

I looked through the \WINCEROOT\...\Intel\PXA27X dir, and found that
display driver used the same ClkMgrReg, of which memory could be mapped
correctly.
Then I changed the register of the ssp/spi driver. I set the "order" to
a big value instead of 0. Now it can be mapped correctly. I wonder
whether it has a dependency to be loaded first.

Many thanks to all again.



Henrik Viklund wrote:
> While I havn't run that exact code snippet myself I'd say VirtualAlloc,
> VirtualCopy and MmMapIoSpace are all pretty thorouhgly tested functions
> ;-) Exactly what do you mean with "found an error"? It dosn't compile?
> It dosn't map right? The SPI port still dosn't work?
>
> Anyway, you'll find all the pxa27x base address definitions and lots of
> other goodies in the pxa27x CSP
> (\WINCE600\PUBLIC\COMMON\OAK\CSP\ARM\INTEL\PXA27X). I think you'll find
> atleast couple of examples of mapping up the clock controller. Good
> luck.
>
> Henrik Viklund
> http:://www.addlogic.se
>
> campos skrev:
>
> > Thanks~
> >
> > I looked the datasheet of PXA270 for the base address:
> > #define BULVERDE_BASE_REG_PA_CLKMGR 0x41300000
> > and I just did what you told me.
> >
> > But it seemed to be an error during the MemMap.
> > I just changed to VirtualAlloc() and VirtualCopy() and I found error in
> > the latter.
> >
> > Would you please give me some hints?
> >
> > Thanks~
> >
> > "Henrik Viklund =D0=B4=B5=C0=A3=BA
> > "
> > > It's pretty trivial, really. You just have to map it up and set the
> > > correct bit in the cken register. Using select pxa27x CSP headers it
> > > could look something like this:
> > >
> > > static XLLP_CLKMGR_T* g_pClkRegs;
> > > ...
> > >
> > > PHYSICAL_ADDRESS ioPhysicalBase =3D {BULVERDE_BASE_REG_PA_CLKMGR,0};
> > > g_pClkRegs =3D (XLLP_CLKMGR_T *)MmMapIoSpace(ioPhysicalBase,
> > > sizeof(XLLP_CLKMGR_T),FALSE);
> > >
> > > ...
> > >
> > > g_pClkRegs->cken |=3D SPIEnableBit;
> > >
> > > ...
> > >
> > > What bit you need to set I leave as an excersise for you to complete
> > > (see the clock manager section in the PXA27x developer's manual...).
> > >
> > > Henrik Viklund
> > > http://www.addlogic.se
> > >
> > >
> > > campos skrev:
> > >
> > > > Windows CE 5.0
> > > > Intel PXA 270
> > > >
> > > > In ssp/spi driver, I want to enable the ssp1 clock, but I don't know
> > > > how to do.
> > > >
> > > > Here is the same problem:
> > > >
> > > > http://groups.google.com/group/microsoft.public.windowsce.platbuild=
er/browse_thread/thread/65e8883348499967/1e88f30d6f9f38a1?lnk=3Dgst&q=3Dclo=
ck+enable+spi&rnum=3D3&hl=3Dzh-CN#1e88f30d6f9f38a1
> > > >
> > > > Can anybody explain it in detail?
> > > >=20
> > > > Thanks in advance!