Why does the AC97 driver configure the GPIO

Hi All,
I am reading the samsung s2440 Ac97 driver.
The AC97 use the IIS bus ,and why does it configure the GPIO as following:

BOOL HardwareContext::AC97_Init()
{

RETAILMSG(AC97_DEBUG,(_T("WAVDEV_AC97::AC97_Init()++\r\n")));

//----- 1. IMPORTANT: By default, the internal clock is disabled. To
configure the controller ------
// we must first enable it.
g_pCLKPWRreg->rCLKCON |= AC97_INTERNAL_CLOCK_ENABLE; // Enable the CPU
clock to the AC97 controller

AC97_GPIO_Init();

v_pAC97regs->rAC_GLBCTRL = 0;
Delay(10); //Sleep(5);

// Write into the AC97 Global Control Register

//Cold Reset
v_pAC97regs->rAC_GLBCTRL = 0x1;
Delay(10); //Sleep(5);
v_pAC97regs->rAC_GLBCTRL = 0x0;
Delay(10); //Sleep(5);

//AC-link On
v_pAC97regs->rAC_GLBCTRL = (1<<2);
Delay(10); //Sleep(5);

//Transfer data enable using AC-link
v_pAC97regs->rAC_GLBCTRL = v_pAC97regs->rAC_GLBCTRL | (1<<3);
Delay(10); //Sleep(5);


// Disable the Codec ready Interrupt
v_pAC97regs->rAC_GLBCTRL = v_pAC97regs->rAC_GLBCTRL | (1<<22);
Delay(10); //Sleep(5);

//while (!(v_pAC97regs->rAC_GLBSTAT& 0x400000));

RETAILMSG(AC97_DEBUG,(_T("WAVEDEV_AC97::AC97 Codec Ready!\r\n")));

v_pAC97regs->rAC_GLBCTRL &= ~(0x400000); // codec ready interrupt disable

Delay(10); //Sleep(5);

v_pAC97regs->rAC_GLBCTRL = (v_pAC97regs->rAC_GLBCTRL & ~(0x3f<<8)) |
0x0000; // PCM_OUT=OFF,PCM_IN=OFF,MIC=OFF;
//v_pAC97regs->rAC_GLBCTRL = (v_pAC97regs->rAC_GLBCTRL & ~(0x3f<<8)) |
0x2200; // PCM_OUT=DMA,PCM_IN=OFF,MIC=DMA;

RETAILMSG(AC97_DEBUG,(_T("WAVDEV_AC97::AC97_Init()--\r\n")));

return TRUE;

}

void AC97_GPIO_Init()
{
//----- 2. Configure the GPIO pins for AC97 mode -----
//
// AC_SDATA_OUT - GPE4
// AC_SDATA_IN - GPE3
// AC_nRESET - GPE2
// AC_BIT_CLK - GPE1
// AC_SYNC - GPE0
//
// Port Init for AC97
//PG[4:0]=AC_SDATA_OUT:AC_SDATA_IN:AC_nRESET:AC_BIT_CLK:AC_SYNC
v_pIOPregs->rGPECON = ((v_pIOPregs->rGPECON & 0xfffffc00) | 0x3ff);
v_pIOPregs->rGPEUP = (v_pIOPregs->rGPEUP & ~(0x1f)) | 0x1f;

}


Many thanks,
Peter

ctacke/>
Sun Jun 18 07:20:04 CDT 2006

I'm not familiar with the S2440, but it's likely that the GPIOs have
multiple functions and, as the comments in the code suggest, they need to be
set up for AC97 mode. Looking in the processor data sheet would probably
tell you this same info.

-Chris


"Peter King" <wangzilue@tom.com> wrote in message
news:Od0tjSqkGHA.2280@TK2MSFTNGP02.phx.gbl...
> Hi All,
> I am reading the samsung s2440 Ac97 driver.
> The AC97 use the IIS bus ,and why does it configure the GPIO as following:
>
> BOOL HardwareContext::AC97_Init()
> {
>
> RETAILMSG(AC97_DEBUG,(_T("WAVDEV_AC97::AC97_Init()++\r\n")));
>
> //----- 1. IMPORTANT: By default, the internal clock is disabled. To
> configure the controller ------
> // we must first enable it.
> g_pCLKPWRreg->rCLKCON |= AC97_INTERNAL_CLOCK_ENABLE; // Enable the CPU
> clock to the AC97 controller
>
> AC97_GPIO_Init();
>
> v_pAC97regs->rAC_GLBCTRL = 0;
> Delay(10); //Sleep(5);
>
> // Write into the AC97 Global Control Register
>
> //Cold Reset
> v_pAC97regs->rAC_GLBCTRL = 0x1;
> Delay(10); //Sleep(5);
> v_pAC97regs->rAC_GLBCTRL = 0x0;
> Delay(10); //Sleep(5);
>
> //AC-link On
> v_pAC97regs->rAC_GLBCTRL = (1<<2);
> Delay(10); //Sleep(5);
>
> //Transfer data enable using AC-link
> v_pAC97regs->rAC_GLBCTRL = v_pAC97regs->rAC_GLBCTRL | (1<<3);
> Delay(10); //Sleep(5);
>
>
> // Disable the Codec ready Interrupt
> v_pAC97regs->rAC_GLBCTRL = v_pAC97regs->rAC_GLBCTRL | (1<<22);
> Delay(10); //Sleep(5);
>
> //while (!(v_pAC97regs->rAC_GLBSTAT& 0x400000));
>
> RETAILMSG(AC97_DEBUG,(_T("WAVEDEV_AC97::AC97 Codec Ready!\r\n")));
>
> v_pAC97regs->rAC_GLBCTRL &= ~(0x400000); // codec ready interrupt disable
>
> Delay(10); //Sleep(5);
>
> v_pAC97regs->rAC_GLBCTRL = (v_pAC97regs->rAC_GLBCTRL & ~(0x3f<<8)) |
> 0x0000; // PCM_OUT=OFF,PCM_IN=OFF,MIC=OFF;
> //v_pAC97regs->rAC_GLBCTRL = (v_pAC97regs->rAC_GLBCTRL & ~(0x3f<<8)) |
> 0x2200; // PCM_OUT=DMA,PCM_IN=OFF,MIC=DMA;
>
> RETAILMSG(AC97_DEBUG,(_T("WAVDEV_AC97::AC97_Init()--\r\n")));
>
> return TRUE;
>
> }
>
> void AC97_GPIO_Init()
> {
> //----- 2. Configure the GPIO pins for AC97 mode -----
> //
> // AC_SDATA_OUT - GPE4
> // AC_SDATA_IN - GPE3
> // AC_nRESET - GPE2
> // AC_BIT_CLK - GPE1
> // AC_SYNC - GPE0
> //
> // Port Init for AC97
> //PG[4:0]=AC_SDATA_OUT:AC_SDATA_IN:AC_nRESET:AC_BIT_CLK:AC_SYNC
> v_pIOPregs->rGPECON = ((v_pIOPregs->rGPECON & 0xfffffc00) | 0x3ff);
> v_pIOPregs->rGPEUP = (v_pIOPregs->rGPEUP & ~(0x1f)) | 0x1f;
>
> }
>
>
> Many thanks,
> Peter
>

Valter
Mon Jun 19 04:49:36 CDT 2006

"Peter King" <wangzilue@tom.com> wrote in
news:Od0tjSqkGHA.2280@TK2MSFTNGP02.phx.gbl:

> Hi All,
> I am reading the samsung s2440 Ac97 driver.
> The AC97 use the IIS bus ,and why does it configure the GPIO as
> following:
[...]


It seems that the same pins can be controlled directly as GPIOs or used
for integrated peripherals I/O and you need to configure them if the
reset default configuration doesn't enable your peripheral I/O (it's a
good idea to configure them anyway, since some other code could had
changed the reset values).



--
Valter Minute
(the reply address of this message is invalid)
(l'indirizzo di reply di questo messaggio non è valido)

Peter
Mon Jun 19 05:03:52 CDT 2006

When I write the MC8051 program,there is buffer to recive or send the date
in the UART communication.And if there is date recived we can read the
buffer directly instead of reading the bit one by one according to the
timing graph.

However,Does the WinCE driver program have the same mechanism as MC8051?
If yes ,generally where is the buffer defined?Is it a register?
For example,the driver of the AC97
,...\WINCE420\PUBLIC\COMMON\OAK\DRIVERS\WAVEDEV\UNIFIED\ENSONIQ\

How does the DMA chip read the media file and render?Is it one bit by one
bit,or read the buffer?

Is it an ISR?

Thanks,
Peter

andyraf
Tue Jun 20 16:02:57 CDT 2006

The WinCE driver uses the DMA controller to stream data out to the codec.
At the driver level, the code just needs to wake up on each interrupt from
the DMA controller and copy a new block of data into the memory region
being used by the DMA controller (this typically happens about once ever
20msec, depending on the size of this region and the rate at which the
codec is being driven. The DMA controller will read (I think) a DWORD at a
time from memory and send it via the serial bus to the codec. Does that
answer your question?

Peter
Tue Jun 20 23:34:45 CDT 2006

<andyraf@microsoft.com>
Thank you for your help.
This is the driver mechanism I want to know.
And wether the rate depends on the interrupt rate or others?
If yes,it's simple for reciving data from the chip pin,
but how about sending data,at which rate,what to depend on?

Thanks again,
Peter
> The WinCE driver uses the DMA controller to stream data out to the codec.
> At the driver level, the code just needs to wake up on each interrupt from
> the DMA controller and copy a new block of data into the memory region
> being used by the DMA controller (this typically happens about once ever
> 20msec, depending on the size of this region and the rate at which the
> codec is being driven. The DMA controller will read (I think) a DWORD at a
> time from memory and send it via the serial bus to the codec. Does that
> answer your question?