I just noticed that the MDCNFG_VAL has changed in XSC1bd.inc. Does anyone
know why? MDCNFG_VAL is the default value for PXA25x SDRAM controller. The
previous setting is CL=3 but now the default is CL=2.
For my platform, SDRAM speeds tops at 100MHz with CL=2 and at 133MHz with
CL=3. I am suspectintg that CL=2 is the main reason why my platform (eboot)
wouldn't start at SDCLK 100MHz. I am hoping that I can fix this problem by
changing the CL to 3.
Regards.
Derek