CE 5.0 Interrupt/Scheduler Question

I have an interrupt that comes in via the FIQ ISR. The IRQ source is masked
and a very small amount of code is executed in the ISR and then the source is
unmasked. There is no subsequent IST to handle this IRQ all processing is
done in the FIQ ISR. The IRQ source (DMA controller) also is set as the
highest priority IRQ in the PXA270 interrupt controller. Well, I should say,
not the highest, the scheduler timer is the highest.

Now, when this DMA interrupt occurs, is the thread that handles the FIQ ISR
scheduled the same (incur the same latencies) as any other scheduled thread
in the system? I would hope not since this is a hardware generated IRQ and
needs to be serviced as quickly as possible but I just want to confirm.

Thanks.

Luca
Mon Apr 28 23:54:50 PDT 2008

it is an interrupt service routine: when the DMA controller triggers its
interrupt, the processor
switches to FIQ mode and fetches code from a the assigned ISR, there is no
scheduling involved.
By the way, usually interrupt controller level registers are programmed in a
way that any pending
interrupt generates an IRQ, so the OS handles their relative priorities; in
this scenario,
the scheduler interrupt is the one with the higher priority. If you program
the controller to generate a FIQ
for the DMA controller, this will be the highest priority interrupt since,
in FIQ has a higher (hardware)
priority level then IRQ; this mean that a DMA interrupt could interrupt the
ISR which handles all the
other interrupts (scheduler included)

--

Luca Calligaris
www.eurotech.it

"FoolBlah" <foolblah@discussions.microsoft.com> ha scritto nel messaggio
news:F2E309F3-BBC8-421E-A030-22DAED2D26E5@microsoft.com...
>I have an interrupt that comes in via the FIQ ISR. The IRQ source is
>masked
> and a very small amount of code is executed in the ISR and then the source
> is
> unmasked. There is no subsequent IST to handle this IRQ all processing is
> done in the FIQ ISR. The IRQ source (DMA controller) also is set as the
> highest priority IRQ in the PXA270 interrupt controller. Well, I should
> say,
> not the highest, the scheduler timer is the highest.
>
> Now, when this DMA interrupt occurs, is the thread that handles the FIQ
> ISR
> scheduled the same (incur the same latencies) as any other scheduled
> thread
> in the system? I would hope not since this is a hardware generated IRQ
> and
> needs to be serviced as quickly as possible but I just want to confirm.
>
> Thanks.

foolblah
Tue Apr 29 03:56:01 PDT 2008

Thanks, that is how I thought (and hoped...) it worked, just had to be sure.

However, I do have a question regarding the FIQ priority. I am running with
a 270 processor, which the IRQ priorities are all configurable. Is the FIQ,
even on the 270, higher priority than the standard IRQ?

The reason I ask is because I know with the 255 processor the only way to
really "prioritize" the interrupts in hardware was to assign them to either
the FIQ for higher priority or the IRQ for lower priority. It is explicitly
stated in the 255 manual that the FIQ IS higher priority than IRQ. But, I do
not see the same explicit explanation of the FIQ versus IRQ priority in the
270 manual so I was not convinced it operated in the same fashion as the 255
processor. Mainly because all of the 270's interrupts are all prioritizable
via the ipr0-39 registers, whereas the 255 has no such feature.

If no one is sure, I will ask Marvell to clear this up for me.

Thanks.

"Luca Calligaris" wrote:

> it is an interrupt service routine: when the DMA controller triggers its
> interrupt, the processor
> switches to FIQ mode and fetches code from a the assigned ISR, there is no
> scheduling involved.
> By the way, usually interrupt controller level registers are programmed in a
> way that any pending
> interrupt generates an IRQ, so the OS handles their relative priorities; in
> this scenario,
> the scheduler interrupt is the one with the higher priority. If you program
> the controller to generate a FIQ
> for the DMA controller, this will be the highest priority interrupt since,
> in FIQ has a higher (hardware)
> priority level then IRQ; this mean that a DMA interrupt could interrupt the
> ISR which handles all the
> other interrupts (scheduler included)
>
> --
>
> Luca Calligaris
> www.eurotech.it
>
> "FoolBlah" <foolblah@discussions.microsoft.com> ha scritto nel messaggio
> news:F2E309F3-BBC8-421E-A030-22DAED2D26E5@microsoft.com...
> >I have an interrupt that comes in via the FIQ ISR. The IRQ source is
> >masked
> > and a very small amount of code is executed in the ISR and then the source
> > is
> > unmasked. There is no subsequent IST to handle this IRQ all processing is
> > done in the FIQ ISR. The IRQ source (DMA controller) also is set as the
> > highest priority IRQ in the PXA270 interrupt controller. Well, I should
> > say,
> > not the highest, the scheduler timer is the highest.
> >
> > Now, when this DMA interrupt occurs, is the thread that handles the FIQ
> > ISR
> > scheduled the same (incur the same latencies) as any other scheduled
> > thread
> > in the system? I would hope not since this is a hardware generated IRQ
> > and
> > needs to be serviced as quickly as possible but I just want to confirm.
> >
> > Thanks.
>
>
>
>

Luca
Tue Apr 29 07:27:24 PDT 2008

The priority relationship between IRQ and FIQ is a characteristic of the ARM
architecture, every chip with an ARM core must respect that specification

--

Luca Calligaris
www.eurotech.it

"FoolBlah" <foolblah@discussions.microsoft.com> ha scritto nel messaggio
news:81EDDB65-3DC6-4082-8866-CC9CC321F913@microsoft.com...
> Thanks, that is how I thought (and hoped...) it worked, just had to be
> sure.
>
> However, I do have a question regarding the FIQ priority. I am running
> with
> a 270 processor, which the IRQ priorities are all configurable. Is the
> FIQ,
> even on the 270, higher priority than the standard IRQ?
>
> The reason I ask is because I know with the 255 processor the only way to
> really "prioritize" the interrupts in hardware was to assign them to
> either
> the FIQ for higher priority or the IRQ for lower priority. It is
> explicitly
> stated in the 255 manual that the FIQ IS higher priority than IRQ. But, I
> do
> not see the same explicit explanation of the FIQ versus IRQ priority in
> the
> 270 manual so I was not convinced it operated in the same fashion as the
> 255
> processor. Mainly because all of the 270's interrupts are all
> prioritizable
> via the ipr0-39 registers, whereas the 255 has no such feature.
>
> If no one is sure, I will ask Marvell to clear this up for me.
>
> Thanks.
>
> "Luca Calligaris" wrote:
>
>> it is an interrupt service routine: when the DMA controller triggers its
>> interrupt, the processor
>> switches to FIQ mode and fetches code from a the assigned ISR, there is
>> no
>> scheduling involved.
>> By the way, usually interrupt controller level registers are programmed
>> in a
>> way that any pending
>> interrupt generates an IRQ, so the OS handles their relative priorities;
>> in
>> this scenario,
>> the scheduler interrupt is the one with the higher priority. If you
>> program
>> the controller to generate a FIQ
>> for the DMA controller, this will be the highest priority interrupt
>> since,
>> in FIQ has a higher (hardware)
>> priority level then IRQ; this mean that a DMA interrupt could interrupt
>> the
>> ISR which handles all the
>> other interrupts (scheduler included)
>>
>> --
>>
>> Luca Calligaris
>> www.eurotech.it
>>
>> "FoolBlah" <foolblah@discussions.microsoft.com> ha scritto nel messaggio
>> news:F2E309F3-BBC8-421E-A030-22DAED2D26E5@microsoft.com...
>> >I have an interrupt that comes in via the FIQ ISR. The IRQ source is
>> >masked
>> > and a very small amount of code is executed in the ISR and then the
>> > source
>> > is
>> > unmasked. There is no subsequent IST to handle this IRQ all processing
>> > is
>> > done in the FIQ ISR. The IRQ source (DMA controller) also is set as
>> > the
>> > highest priority IRQ in the PXA270 interrupt controller. Well, I
>> > should
>> > say,
>> > not the highest, the scheduler timer is the highest.
>> >
>> > Now, when this DMA interrupt occurs, is the thread that handles the FIQ
>> > ISR
>> > scheduled the same (incur the same latencies) as any other scheduled
>> > thread
>> > in the system? I would hope not since this is a hardware generated IRQ
>> > and
>> > needs to be serviced as quickly as possible but I just want to confirm.
>> >
>> > Thanks.
>>
>>
>>
>>