Re: Help required with PlatBuilder 5.0 on PXA255 by Dean
Dean
Tue Aug 29 08:40:58 CDT 2006
The only thing I noticed in the config files is an invalid size in your
config.bib RAM section. I don't know that this would cause a problem, but
it should be 64K aligned. However this shouldn't be relevant for turning on
the MMU. How do you know that you can't turn on the MMU? Note that you
can't step through this code with a jtag debugger...
--
Dean Ramsier - eMVP
BSQUARE Corporation
"grolo" <kthamm@xpaneon.de> wrote in message
news:1156851800.431168.151980@p79g2000cwp.googlegroups.com...
> Then tell me which information is required ? Want the TLB ? The config
> BIB ?
>
> think these files are the ones which are essential for the problem. I
> did not author them ... I just copied them from the old (Working) CE4.2
> code. It can't be something big, because it works on CE 4.2.
>
> ----- BOOTLOADER START IMAGE CODE
> TEXTAREA
>
> EXPORT RetrieveStackPointer
> IMPORT WriteString
>
> LEAF_ENTRY RetrieveStackPointer
>
> mov r0, sp
> mov pc, lr
>
> LEAF_ENTRY Launch
> ldr r2, =PhysicalStart
>
> ldr r3, =0x00FFFFFF
> and r2, r2, r3 ; Mask off high 3 bits for physical
> address
> orr r2, r2, #0xA0000000 ; Add Physical Base of SDRAM bank 0
> ; PhysicalStart Label is always in RAM
>
> mov r1, #0x0078 ; Disable MMU
> mcr p15, 0, r1, c1, c0, 0
>
> nop
> mov pc, r2 ; Jump to PStart
>
> nop ; These NOPs are used to flush the
> Pipeline
> nop
> nop
> nop
>
>
> ; MMU & caches now disabled.
>
> PhysicalStart
>
> mov r2, #0 ; get a zero to turn things off
>
> mcr p15, 0, r2, c8, c7, 0 ; flush (invalidate) I/D tlb's
>
> mcr p15, 0, r2, c7, c7, 0 ; flush (invalidate) I/D caches
>
> mcr p15, 0, r2, c7, c10, 4 ; Drain the write buffer
>
> nop
> nop
> nop
>
>
>
> mov r11, r0 ; Save OEMMemoryMap to r11
>
>
> add r0, pc, #LaunchMsg-(.+8)
> bl WriteString
>
> mov r0, r11
>
>
> mov pc, r0 ; Jump to program we are launching.
>
> ----- END BOOTLOADER START IMAGE CODE
>
>
> Ignore 'Stron Arm' Comments here ... this is Copy pase code, that works
> on WinCE4.2
>
> ----- STARTUP.S
> OPT 2 ; disable listing
> INCLUDE kxarm.h
>
> OPT 1 ; reenable listing
> OPT 128 ; disable listing of macro expansions
>
>
> RTCrcnr EQU 0x90010004 ; RTC count register
> RTCrcnrAdjust EQU 216 ; RTC count reset adjustment
>
> OSCR EQU 0x40A00010 ; OS timer counter register
>
> MDCNFG EQU 0x48000000 ; SDRAM configuration register 0
> MDREFR EQU 0x48000004 ; SDRAM refresh control register
> MDMRS EQU 0x48000040 ; MRS value to be written to SDRAM
>
>
> PWRMODE_SLEEP EQU 3
>
> MEMC_BASE_U_VIRTUAL EQU 0xA6100000
> MDREFR_OFFSET EQU 0x4
> MDREFR_APD EQU 0x00100000
>
> BOOT_FLASH_BASE_U_VIRTUAL EQU 0xA0000000
>
> IMPORT KernelStart
> IMPORT OEMInitDebugSerial
> IMPORT BacklightBreakPhys
>
> STARTUPTEXT
> LEAF_ENTRY StartUp
>
> IF :DEF: BOOTLOADER
> ; Initialize the Strong ARM processor
>
> add r0, pc, #ProcessorInitTable-(.+8)
> mov r3, #ProcessorInitSize ; (r3) = # of registers to
> initialize
> 10 ldmia r0!, {r1,r2}
> str r2, [r1]
> subs r3, r3, #1
> bne %B10 ; loop thru the table
> nop
> ; RTC clocks at CPU speed on reset, subtract out amount it
> ; incremented until trim register set so time will not jump
> ; ahead on warm reset
> ;ldr r0, =RTCrcnr
> ;ldr r1, [r0]
> ;sub r1,r1,#RTCrcnrAdjust
> ;str r1, [r0]
>
> ;
> ; Move the Physical RAM base into r0:
> ;
>
> ENDIF
>
> IF :DEF: MEMSRAM
> mov r0, #0x08000000
> ELSE
> mov r0, #0xa0000000
> ENDIF
> add sp, r0, #0x10000 ; temp stack for initialization
>
>
> bl InitSerial
>
> ;mov r0, #0x40
> ;bl WriteByte
>
>
> add r0, pc, #HelloMsg-(.+8)
> bl WriteString
>
>
>
>
> IF :DEF: BOOTLOADER
>
> ;
> ; Perform StrongARM specific initialization.
> ;
>
>
> ldr r3, =OSCR ; reset the OS Timer Count to zero
> mov r2, #0
> str r2, [r3]
> ldr r4, =0x300 ; really 0x2E1 is about 200usec,
> so 0x300 should be plenty
> 10
> ldr r2, [r3]
> cmp r4, r2
> bgt %B10
>
> ; ** Dev Manual sect. 5.14 step 3
> -- (Skip if no SDRAM)
> ldr r3, =MDREFR
>
>
> mov r2, #0x018 ; Set a valid SDRAM Refresh Interval (DRI)
> ;orr r2, r2, #0x20000 ; configure K1DB2 and K2DB2 (not needed since
> they are 0)
> orr r2, r2, #0x400000 ; Add SLFRSH Bit (will be cleared later on)
> str r2, [r3] ; store it
>
> orr r2, r2, #0x00010000 ; assert K1RUN for SDCLK1
> str r2, [r3] ; change from "self-refresh and
> clock-stop" to "self-refresh" state
>
> bic r2, r2, #0x00400000 ; clear SLFRSH bit field
> str r2, [r3] ; change from "self-refresh" to
> "Power-down" state
>
> orr r2, r2, #0x00008000 ; set the E1PIN bit field
> str r2, [r3] ; change from "Power-down" to
> "PWRDNX" state
>
> nop ; no action is required to change
> from "PWRDNX" to "NOP" state
>
> ; ** Dev Manual sect. 5.14 step 4
> -- (Skip if no SDRAM)
> ldr r3, =MDCNFG ; Load the SDRAM Configuration
> register. Must not be enabled yet.
> ;ldr r2, =0x000009C8 ; Generated value
> ldr r2, =0x000019C8 ; Generated value (CL2,
> SLOW)(SA1111_Adrr Mode)
> str r2, [r3] ; Write to MDCNFG register
>
> ; ** Dev Manual sect. 5.14 step 5
> -- (Skip if no SDRAM)
> ;---- Wait 200 usec
> ldr r3, =OSCR ; reset the OS Timer Count to zero
> mov r2, #0
> str r2, [r3]
> ldr r4, =0x300 ; really 0x2E1 is about 200usec,
> so 0x300 should be plenty
> 10
> ldr r2, [r3]
> cmp r4, r2
> bgt %B10
>
> ; ** Dev Manual sect. 5.14 step 6
> -- (Skip if no SDRAM)
> ; make sure the DCACHE is off
> before step 7
> ; this should not be need if used
> out of reset.
>
> ; ** Dev Manual sect. 5.14 step 7
> -- (Skip if no SDRAM)
> ldr r3, =0xA0000000
> mov r2, #8 ; now must do 8 refresh or CBR
> commands before the first access
> CBR_refresh1
> str r3, [r3]
> subs r2, r2, #1
> bne CBR_refresh1
>
> ; ** Dev Manual sect. 5.14 step 8
> ; can re-enable DCACHE if it was turned off in step 6
>
> ; ** Dev Manual sect. 5.14 step 9
> ldr r3, =MDCNFG ; sdram config -- sdram enable
> ldr r2, [r3]
> orr r2, r2, #0x00000001 ; enable appropriate banks, value
> depends on selected banks
> str r2, [r3] ; write to MDCNFG
>
> ; ** Dev Manual sect. 5.14 step 10
>
> ldr r3, =MDMRS ; write the MDMRS
> ldr r2, =0x00020022 ; the writable bits will be
> written as a 0
> str r2, [r3]
>
>
> add r0, pc, #SDRAMInitMsg-(.+8)
> bl WriteString
>
>
> ENDIF
>
>
>
> ;mcr p15, 0, r0, c15, c1, 2 ; enable clock switching
>
> ;INCLUDE map1100.h
>
> ;adr r0, OEMAddressTable ; (r0) = physical address of OEMAddressTable
> add r0, pc, #OEMAddressTable-(.+8) ; (r0) = physical address of
> OEMAddressTable
>
> ;b BacklightBreakPhys
>
> bl KernelStart
>
>
> ;
> ; KernelStart should never return:
> ;
>
> spin b spin
> ----- END STARTUP.S
>
> get stuck in here:
> ----- ARMTRAP.S .... (Windows Private Code)
> ; The page tables and exception vectors are setup. Initialize the MMU
> and turn it on.
>
> ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
>
> mov r1, #1
> mtc15 r1, c3 ; Setup access to
> domain 0 and clear other
> ; domains including 15
> for PSL calls (see above)
> mtc15 r10, c2
>
> mov r0, #0
> mcr p15, 0, r0, c8, c7, 0 ; Flush the I&D TLBs
>
> mfc15 r1, c1
> orr r1, r1, #0x007F ; changed to
> read-mod-write for ARM920 Enable: MMU, Align, DCache, WriteBuffer
> orr r1, r1, #0x3200 ; vector adjust,
> ICache, ROM protection
> ldr r0, VirtualStart
> cmp r0, #0 ; make sure no stall on
> "mov pc,r0" below
>
> mtc15 r1, c1 ; enable the MMU &
> Caches
> mov pc, r0 ; & jump to new
> virtual address
>
> <<<<<<<<< LAST FUNCTIONAL STATEMENT >>>>>>>>>
>
>
> nop
>
> ;
>
>
> ; MMU & caches now enabled.
> ;
> ; (r10) = physcial address of 1st level page table
>
> VStart ldr sp, =KStack
> add r4, sp, #KData-KStack ; (r4) = ptr to
> KDataStruct
> mov r0, #0x80000000
> str r0, [r4, #hBase] ; set HandleBase
> ldr r0, =DirectRet
> str r0, [r4, #pAPIReturn] ; set DirectReturn
> address
>
> ----- END ARMTRAP.S
>
> ----- OEMAddressTable
> OEMAddressTable
>
> ;;;-------------------------------------------------------------
> ;;; Virt Addr Phys Addr MB
> ;;;-------------------------------------------------------------
>
> DCD 0x8C000000, 0xA0000000, 64 ; 0-64 MB of onModule SDRAM (/S0)
> (Main Memory/RAMIMAGE) -> config.bib
> DCD 0x80000000, 0x00000000, 16 ; 0-64 MB of onModule Flash (CS0)
> (FLASHIMAGE)
> DCD 0x81000000, 0x04000000, 16 ; 0-64 MB of onModule Flash (CS1)
> (FLASHIMAGE)
>
> DCD 0x84000000, 0x20000000, 1 ; 1 MB PCMCIA Socket0 I/O
> DCD 0x84100000, 0x28000000, 1 ; 1 MB PCMCIA Socket0 Attr
> DCD 0x84200000, 0x2C000000, 1 ; 1 MB PCMCIA Socket0 Mem
> DCD 0x84300000, 0x30000000, 1 ; 1 MB PCMCIA Socket1 I/O
> DCD 0x84400000, 0x38000000, 1 ; 1 MB PCMCIA Socket1 Attr
> DCD 0x84500000, 0x3C000000, 1 ; 1 MB PCMCIA Socket1 Mem
>
> DCD 0x84600000, 0x0C000000, 1 ; 1 MB CPLD memory interface (CS3)
> DCD 0x84700000, 0x10000000, 1 ; 1 MB USBHOST memory interface (CS4)
> DCD 0x84800000, 0x14000000, 1 ; 1 MB EXAR UART memory interface
> (CS5)
>
> DCD 0x86000000, 0xE0000000, 1 ; 1 MB Zero Bank
> DCD 0x86100000, 0x48000000, 1 ; 1 MB Memory Controller Registers
> DCD 0x86200000, 0x40000000, 32 ; 32 MB Peripheral Registers
> DCD 0x88200000, 0x44000000, 1 ; 1 MB LCD Controller Registers
>
>
> DCD 0x00000000, 0x00000000, 0 ; End of Table (MB MUST BE ZERO!)
>
> END
>
> ----- END OEMAddressTable
>
> ----- Config.bib
> AUD_DMA 8c000000 00004000 RESERVED
> SER_DMA 8c004000 00004000 RESERVED
> USB_DMA 8c008000 00004000 RESERVED
> DRV_GBL 8c00C000 00004000 RESERVED
>
> DISPLAY 8c010000 00100000 RESERVED
> NK 8E000000 01A00000 RAMIMAGE ; 26 MB
> RAM 8C110000 01eECA00 RAM ; 32MB SDRAM - 1MB FrameBuffer
> ; 8DFD'A000 8DFF'FFFF 152k 0002'6000 Bootloader Framebuffer
> RESERVED
>
> COMPRESSION=ON
> PROFILE=OFF
> KERNELFIXUPS=ON
>
> FSRAMPERCENT=0x80808080
>
> ; if you want to copy the code from flash to ram
> ; set IMGFLASH to nothing and FLASHSHADOW to 1
>
> ; image copy code is done in bootloader
> <<<< THIS WORKS !! >>>>
> ; 8E000000 + F2020000 = 80020000
> ROMOFFSET=0xF2020000
>
> ----- END Config.bib
>
> Dean Ramsier wrote:
>> Not intended to be a smart statement - I'm telling you what the problem
>> is
>> based on my considerable experience. Since you haven't provided any
>> other
>> information, there is no other detail we can give.
>>
>> Sorry...
>>
>> --
>> Dean Ramsier - eMVP
>> BSQUARE Corporation
>>
>>
>> "grolo" <kthamm@xpaneon.de> wrote in message
>> news:1156758244.389090.12400@p79g2000cwp.googlegroups.com...
>> >
>> > Dean Ramsier wrote:
>> >> It's either a problem with your config files or a problem with your
>> >> hardware - always. Just because you haven't seen a problem doesn't
>> >> mean
>> >> there isn't one :)
>> >
>> > Well yes, there is one - I was able to detect that so far... the device
>> > does not switch the MMU to Kernel Mode :)
>> >
>> > The problem is that I am not able to locate it .... that's why I am
>> > asking for help. I don't need help for a problem that I am able to
>> > solve by myself.
>> >
>> > Especially sentences like this are not very helpful, they are contra
>> > productive:
>> >
>> >> It's either a problem with your config files or a problem with your
>> >> hardware - always.
>> >
>> > There might be ppl who are a bit more experienced than me. I am not
>> > asking for help to get told that I have a problem with some smart
>> > statements. That's what I know and that's why I am posting here.
>> >
>