Dear Greats,
We are using DBAu1200 reference platform with LB104S01-TL01 LVDS
display connected. By modifying the display driver settings we are able
to see the display.
In the display we are able to see lot
of flickering. This is due to improper configuration of display
controller
values. We need the specific parameter values from LG to support AMD
Au1200
LCD controller.
Find the below settings, that we configured
(WINCE500\PLATFORM\Db1200\Drivers\Display\Au1200lcd\lcdgpe.cpp file) to
bring up the display.
============================================================================
=================================================
{ TEXT("800x600_TFT"),
800, 600,
/* mode_screen */ LCD_SCREEN_SX_N(800) |
LCD_SCREEN_SY_N(600),
/* mode_horztiming */ LCD_HORZTIMING_HPW_N(12) |
LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(2),
/* mode_verttiming */ LCD_VERTTIMING_VPW_N(2) |
LCD_VERTTIMING_VND1_N(2) | LCD_VERTTIMING_VND2_N(5) ,
/* mode_clkcontrol */ LCD_CLKCONTROL_PCD_N(1),
/* mode_pwmdiv */ 0x8000063f,
/* mode_pwmhi */ 0x03400000,
/* mode_outmask */ 0x00fcfcfc,
/* mode_fifoctrl */ 0x2f2f2f2f,
/* mode_toyclksrc */ 0x00000004,
/* mode_backlight */ 0x00000000,
/* mode_auxpll */ 96/12,
/* mode_bitmask */ &RGB565,
},
============================================================================
=================================================
We have set the below settings, referring LG LCD and Au1200 data sheet.
1. Screen resolution
- 800x600
2. Horizontal Sync Pulse Width in Pixels. - 13
3. Horizontal Non Display Period 1 in Pixels. - 14
4. Horizontal Non Display Period 2 in Pixels. - 3
5. Vertical Sync Pulse Width in Lines
- 3
6. Vertical Non Display Period 1 in Lines. - 3
7. Vertical Non Display Period 2 in Lines. - 6
8. Pixel Clock Divisor (PCD)
- 1
9. Auxiliary PLL multiplier
- 8
The DCLK clock for LG is ranging from 37 to 40 MHz, formula we refer
was
1. Auxiliary PLL clock freq/(2 *(PCD+1) = (37 to 40) MHz
2. Auxiliary PLL clock freq = Auxillary PLL multiplier * 12 MHz (OSC
Freq)
We configured Auxiliary PLL clock freq as 96 MHz (12*8) and PCD as 1 to
get
24 MHz as DCLK (Which is less than the minimum value 37).
To match the 39-40 MHz required we increase the AuxPLL to 156, but this
is
moving display in to VGA mode, no screen is seen in the LVDS display.
Not able to indentify the root cause of this. We are trying to verify
the clocks physically, before that I thought of posting this
information for some help.
Kindly any can help us to solve the problem
avkumar