Cache eviction avoidance

Hi all,
I am working on Wince5.0 on Arm920 processor board. I am trying to
lock a certain set of data in the cache and complete my processing.
But I suppose that the data that is locked is getting evicted during
context switching. Is their any way to avoid this cache flushing in
WINCE. In which part of the code is the cache flushing implemented in
the OS.
Do anyone knows any other best way of cache usage in WINCE5.0?

Regards
Pradeep

Michel
Thu Jun 12 21:01:13 PDT 2008

Can you tell us *why* you want to do this?

(See also http://guruce.com/blogpost/howtoaskquestionsonnewsgroups)

Good luck,

Michel Verhagen, eMVP
Check out my blog: http://GuruCE.com/blog

GuruCE Ltd.
Microsoft Embedded Partner
http://GuruCE.com
Consultancy, training and development services.

deepu wrote:
> Hi all,
> I am working on Wince5.0 on Arm920 processor board. I am trying to
> lock a certain set of data in the cache and complete my processing.
> But I suppose that the data that is locked is getting evicted during
> context switching. Is their any way to avoid this cache flushing in
> WINCE. In which part of the code is the cache flushing implemented in
> the OS.
> Do anyone knows any other best way of cache usage in WINCE5.0?
>
> Regards
> Pradeep

deepu
Thu Jun 12 22:06:15 PDT 2008

I am looking for a better performance in processing. I am doing an FFT
processing on a junk of data. When i saw from the profiler in RVDS,
got that cache missrate is too much effective in my program. Hence I
wanted to lock the array in the cache before performing my operation.

Regards
Pradeep

Michel
Thu Jun 12 23:09:45 PDT 2008

Ok, AFAIK there's no standardized way to lock (part of) the cache, but
you may be able to create such functionality yourself. There's been
quite a bit of discussion on this in the past:
http://groups.google.com/groups?as_q=lock+cache&num=10&scoring=r&hl=en&as_epq=&as_oq=&as_eq=&as_ugroup=*windowsce*&as_usubject=&as_uauthors=&lr=&as_drrb=q&as_qdr=&as_mind=1&as_minm=1&as_miny=1981&as_maxd=13&as_maxm=6&as_maxy=2008&safe=off

I hope that helps!

Good luck,

Michel Verhagen, eMVP
Check out my blog: http://GuruCE.com/blog

GuruCE Ltd.
Microsoft Embedded Partner
http://GuruCE.com
Consultancy, training and development services.

deepu wrote:
> I am looking for a better performance in processing. I am doing an FFT
> processing on a junk of data. When i saw from the profiler in RVDS,
> got that cache missrate is too much effective in my program. Hence I
> wanted to lock the array in the cache before performing my operation.
>
> Regards
> Pradeep

deepu
Thu Jun 12 23:43:21 PDT 2008

I am afraid a already had looked into it before updating my post.
All of them are on instruction cache. I am looking for datacache
locking.

How about using "_prefetch" function alone, any one has any idea of
using it.

Regards
Pradeep

Silver
Fri Jun 13 15:44:53 PDT 2008

Grab the ARM920 core manual (from arm.com) and you will find the
instructions for manipulating cache. You will need to know how your cache
architecture is setup, that is lines/ways/tagging type. You will need to use
assembler routines to do that.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0151c/ARM920T_TRM1_S.pdf

Your cache is most likely 4 ways, 32 bytes per line, physically tagged.

Register 7 is for cache operations reg, and reg 9 is for locking it.


"Example 2.2. Load a cache line into DCache line 0 and lock it down

MCR to CP15 register 9, opcode_2 = 0x0, Victim=Base=0x0

Data load (LDR/LDM). Assuming the DCache misses, a linefill occurs to line
0.

MCR to CP15 register 9, opcode_2 = 0x0, Victim=Base=0x1

More DCache linefills now occur into lines 1-63."

Do not forget to undo the locks when you are done.

Note that using a profiler will have a side effect of hitting the cache to
run the profiler code, to be careful with those reults.

That said:
I very much doubt that you will see much improvement unless you are *very*
careful.

Silver
--

Steve
Fri Jun 13 15:58:29 PDT 2008

If you are doing an FFT, are you sure that your data will fit into the
cache? Maybe cache paging is expected do to the data size and/or the way you
walk through the data.

"deepu" <pradeepit@gmail.com> wrote in message
news:f9b9097c-70a0-4512-929d-adc677ccfe8c@d45g2000hsc.googlegroups.com...
>I am afraid a already had looked into it before updating my post.
> All of them are on instruction cache. I am looking for datacache
> locking.
>
> How about using "_prefetch" function alone, any one has any idea of
> using it.
>
> Regards
> Pradeep

deepu
Mon Jun 16 06:27:20 PDT 2008

Dear silver,
I have already tried this method, and have no luck.
Hence i was asking for methods to be carefull enough. What all should
be considered during this lock process. From whatever the inputs I
have got, cache flushing cause a main problem during "lock" in wince.
In that case how do I avoid such instances.

Regards
Pradeep